<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom" xmlns:content="http://purl.org/rss/1.0/modules/content/"><channel><title>Compilers on Hanh Pham's Blog</title><link>https://hanhpham.vercel.app/tags/compilers/</link><description>Recent content in Compilers on Hanh Pham's Blog</description><generator>Hugo</generator><language>en-us</language><lastBuildDate>Thu, 01 Oct 2026 10:00:00 +0700</lastBuildDate><atom:link href="https://hanhpham.vercel.app/tags/compilers/index.xml" rel="self" type="application/rss+xml"/><item><title>The ISA Is a Contract, Not a Benchmark: What the Instruction Set Still Costs You in 2026</title><link>https://hanhpham.vercel.app/posts/isa-as-a-contract-risc-vs-cisc/</link><pubDate>Thu, 01 Oct 2026 10:00:00 +0700</pubDate><guid>https://hanhpham.vercel.app/posts/isa-as-a-contract-risc-vs-cisc/</guid><description>Four decades of micro-op convergence absorbed the classic textbook differences between RISC and CISC, but the instruction set still bills you in three places you cannot optimize away: memory ordering contracts, frontend silicon budgets, and ecosystem sovereignty.</description></item></channel></rss>